Currently, in consideration of the cost, the liquid crystal display module of high resolution (VGA or higher resolution) is not configured with a built-in frame buffer. Thus, the liquid crystal display module is required to continuously receive a sequence of display frames through a display interface at a certain rate. In the prior art, the rate is generally a fixed rate, that is, the display controller sends pixels to the display interface of the liquid crystal display at the configured fixed pixel rate. An access controller for a memory will authorize read/write rights to a display channel and other main channels accessing the memory based on a read/write efficiency first principle or a display highest priority principle. When the access controller for the memory uses an efficiency first arbitration policy to allocate a display bandwidth to the display channel, if there are heavy memory access loads in a period of time, it is not guaranteed that the display channel obtains enough memory bandwidth, possibly leading to the display image misalignment. When the access controller for the memory uses a priority arbitration policy and grants the display channel the highest priority, although the display image misalignment caused by the fact that the display channel cannot obtain enough bandwidth is avoided, serious bandwidth waste is brought to the memory access (low access efficiency), thus increasing the memory access power consumption.